One of the biggest talking points regarding the AMD Athlon is its use of the Alpha EV6 bus protocol in place of the current GTL+ protocol as used by Intel. The EV6 allows a number of advantages for the Athlon in that it allows the chipset to run various parts of the bus asynchrously. This means that although the main front side bus runs at a speed of 200 MHz, the main system memory can run at a separate speed, allowing for the fitting of PC-100 or PC-133 SDRAM into Athlon systems.

This is achieved by the EV6 bus only in fact being the protocol used between the chipset and CPU. All other areas such as the memory and PCI bus can in fact be given a separate pipeline from the chipset (or however the chipset designer see’s fit). As the EV6 itself is only concerned with the CPU to chipset interface, companies such as VIA and Ali are able to design Athlon chipsets relatively easily as all they need to do is engineer an EV6 bus onto an existing P6 chipset. This is rumoured as to what VIA have done with the Apollo Pro Athlon chipset.

The main advantage of the EV6 bus though will not be exploited on a uni-processor system, but will only be of use when chipsets supporting dual CPU running appear. This centres around the EV6's “Point to Point” topology, which means that each CPU is given a separate pipeline to the chipset. This means that when 2 CPU’s are used they can both utilise their own 1.6 Gb of bandwidth between the CPU and chipset. When a second CPU is added to the system, the amount of bandwidth per CPU does not diminish. This compares favorably to the GTL+ protocol which forces all CPU’s to share bandwidth between the CPU and chipset, meaning that when a second CPU is added the bandwidth available to both CPU’s is halved. The EV6 means that AMD’s Athlon has a big advantage over the Pentium III and Xeon processors when it comes to multi-processor systems.

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