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AMD Duron

64 Kb integrated Level 2 cache.

Like the Athlon "Thunderbird", the Duron's Level 2 cache arrangement is the key to it's performance. Unlike Intel's latest Celeron processor, the Duron features a Level 2 cache arrangement which doesn't disable any of the features originally designed into the Athlon "Thunderbird"/Duron architechtures.

The Duron features a full speed on-chip mounted Level 2 cache similar to that of the Athlon "Thunderbird". The only difference between the Duron and it's larger sibling is the size of this level 2 cache. Whereas the Athlon "Thunderbird" features 256 Kb of on-chip Level 2 cache the Duron only features a small 64 Kb Level 2 cache. This is a far smaller amount than that found on previous AMD designs which incorporated an on-chip cache architecture such as the K6 III and Athlon "Thunderbird" which both feature 256 Kb. 64 Kb also seems small when compared to the 128 Kb found on Intel's Celeron processor.

The Duron does though still feature the large 128 Kb Level 1 cache as has been found on all processors based upon AMD's K7 (Athlon K7 & K75, Athlon "Thunderbird" and Duron) core design. This has a large effect upon performance, especially when compared to the 32 Kb found on Intel's P6 processor architecture (Pentium II/III, Celeron, etc), especially it's main rival the FC-PGA Celeron.

The Duron, like the Athlon "Thunderbird" and K6 III all feature a 64-bit memory interface between the CPU and Level 2 cache. This does not contrast well with Intel's "Coppermine" Pentium III and FC-PGA Celeron designs which feature a 256-bit interface between the Level 2 cache and CPU.

Unfortunately AMD have not followed Intel into equipping either the Duron or the Athlon "Thunderbird" with an ultra-low latency design for their level 2 cache architectures. Both the Athlon and Duron feature a Level 2 cache latency of 13 clock cycles, compared to a low 7 cycles of Intel's "Coppermine" Pentium III and FC-PGA Celeron processors. Can this be seen as a lost opportunity for AMD to have equipped it's Duron and Athlon "Thunderbird" designs with a low latency cache? It would surely have boosted their performance, but it may have come at a cost of lower yields on both designs.

Although the Duron features a small Level-2 cache of only 64 Kb, AMD have been able to take advantage of the Exclusive Cache architchture to get around what at first seems a disadvantage. When compared to Intel's Celeron which features an Inclusive Cache architecture, the Duron's small Level 2 cache is not such as disadvantage. Here is our explanation of Exclusive and Inclusive cache borrowed from our Athlon "Thunderbird" article:

"Exclusive Level 2 cache sees no duplication of data between the 128 Kb Level 1 and 256 Kb Level 2 cache of the "Thunderbird". This uses the Level 2 cache essentially as an overflow from the processors Level 1 cache. For all intents and purposes we can view both the Level 1 and and Level 2 cache of the Athlon "Thunderbird" as 384 Kb of unified cache as this is how it is used (in simple terms). This can be compared to the Inclusive Level 2 cache of older Athlon processors, where the contents of the Level 1 cache would be directly mapped to the Level 2 cache thus using up 128 Kb of it. Although there would be a total of 640 Kb cache available, the system would only be able to use 512 KB due to the duplication of data in the Level 2 cache. "

Again we see a similar process at work with the Duron and Celeron processors.

The Duron uses a large Level 1 cache of 128 Kb and a small Level 2 cache of 64 Kb. Crucially these can be combined into a large unified cache area of 196 Kb. The Celeron on the other hand has a small Level 1 cache of 32 Kb and a larger Level 2 cache of 128 Kb which cannot be combined. In fact as the Celeron uses an inclusive cache, the direct mapping of the contents of the 32 Kb Level 1 cache to the Level 2 cache means that only 96 Kb is available for additional data to be loaded after Level 1. This gives the Celeron a total amount of cacheable memory of 128 Kb (we can read the size of the Level 2 as the total area in an inclusive cache). This has a direct effect upon the Celeron as a Level 2 cache miss will occur at a much earlier point than it does on the Duron, thus requiring a request for data from the main system memory.

Again we can see yet another advantage of the Duron here, as the Celeron's lower cache miss threshold means that it will have to perform a read from system memory. Combine this with the slow 66 MHz (66 MHz SDRAM) bus used by the Celeron, as opposed to the 200 MHz (DDR) (PC-100/133 SDRAM) bus of the Duron, a performance gap begins to emerge between the Intel and AMD chips."

Chipsets & Boards.

The Duron is compatible with the same chipsets that are used by it's larger sibling, the Athlon "Thunderbird" as they both share the same Socket A interface. This means that the Duron can be used with VIA's new KT133 chipset along with the KM133 and KL133 chipsets which feature integrated graphics.

As the Duron is being sold as AMD's budget CPU, expect many to be used with VIA's KM133 and KL133 chipsets. Both of these chipsets featre integrated graphics from S3 which will enable system integrators to drive down the cost of their machines. The KM133 differs from the KL133 in that it will feature an external AGP 4X slot whereas the KL133 does not.

Both the KM133 and KL133 chipsets feature the 2D core of S3's Savage 2000 graphics controller paired with the 3D controller from the Savage 4 Pro. This should give users very good 2D graphics under Windows and reasonable 3D performance for gaming. Our opinion is that both the KM133 and KL133 chipsets could well benefit from the 3D core of the Savage2000 in place of that of the Savage 4 Pro.

Motherboard support at the time of writing looks as if it will be good. Most of the major motherboard vendors are planning to offer Socket A based motherboards based upon VIA's family of chipsets. At the time of writing most motherboards have been delayed due to VIA holding back supplies of chipsets briefly for validation purposes.

Duron - Page 1.

Duron - Page 3.

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